DEVIN K. BROWN

EDUCATION:

6/95 Master of Science in Electrical Engineering, Georgia Tech

6/93 Bachelor of Electrical Engineering with High Honor, Georgia Tech

EXPERIENCE:

2002 - present: Senior Research Engineer, Microelectronics Research Center, Georgia Tech, Atlanta, Georgia

§         responsible for operation, training and process development of $6M JEOL JBX-9300FS 100kV direct write electron beam lithography (EBL) system

§         achieved 6.5nm resolution in hydrogen silsesquioxane negative electron beam resist

§         developed EBL process for carbon nanotube growth catalyst, successfully growing vertical and horizontal single walled nanotubes, combining photolithography pattern definition on EVG 620 Mask Aligner with EBL processing

§         developed EBL baseline processes and training program for over 39 internal and external (SEMATECH, Applied Micro Optics, Novellus, Nano and Micro Technology Consultants) research groups enabling their research goals.  work consists of characterizing ebeam exposure of five different resists, and supporting processes such as metal evaporation, plasma etching, etc.

§         developed nanometer scale silicon etching using Plasma-Therm ICP chlorine etching to produce 70nm lines with 80nm space with anisotropic 3:1 aspect ratio.

§         support advanced nanoindentation measurements of nanometer scale film stress, hardness, and modulus characterization as well as MEMS characterization and advanced electro-optical I/O utilizing Hysitron Triboindenter.

§         developed process for fabricating sub-micron chrome quartz photomasks

§         main support for KLA P15 contact profilometer and Unifilm metal sputter deposition.  oversee trainers and application support

§         supported evaluation of advanced field emission SEM acquisition

§         implemented CMOS device characterization & test automation on Alessi Cascade probe station.

§         develop lab safety training materials, courses, and instruction

1997 – 2002: Senior Etest Device Engineer, Logic Technology Development, Intel, Hillsboro, Oregon

• Evaluated semiconductor fab process conditions and used device physics knowledge to optimize CMOS transistor ION/IOFF performance to maximize Pentium family microprocessor operating frequencies (> 2 GHz)
• Using Cadence Opus, coordinated layout and development of CMOS semiconductor devices for monitoring product and process design rule health (DRC, Hercules)
• Identified problems with photolithography patterning using due to optical proximity correction (OPC) algorithm errors using fracturing software (CATS) in order to improve transistor performance on small feature devices.
• Provided feedback to VLSI design engineers on semiconductor process impacts/limitations on performance of new product introductions (NPI)
• Helped qualify and analyze process window for new Cobalt salicide process for 70 nm linewidths.
• Performed front end transistor (0.13 µm, 18Å oxide) and back end 6 metal layer parametric design rule analysis in order to qualify and characterize new processes (DOE).
• Performed root cause analysis of Etest parametric failures and used multivariate analysis to identify responsible semiconductor fab process operations in order to continuously improve line yield and ensure quality and reliability.
• Used general statistic skills to monitor and control process health (SPC)
• Developed empirical model to predict microprocessor frequencies 6 weeks before product completed allowing quick response to in fab excursions.

1997 - 1998: Course Instructor, Portland Community College, Hillsboro, OR

§         while working at Intel, taught part time college level instruction of fundamental Boolean algebra and digital electronics to 10-15 students per quarter both in a classroom and laboratory setting.

1995 – 1997: Ion Implant Process Engineer, Technology Manufacturing Group, Intel, Aloha, OR

§         Qualified Varian E500 and 180XP Ion Implanters for bipolar & CMOS process using metrology such as SIMS, V/I, and Therma-wave

§         Managed individuals and teams to meet IC manufacturing output, yield goals, while properly planning and executing area improvement projects. Met ISO 9002 certification and criteria.

§         Worked with E-test and Integration engineers to solve semiconductor device performance problems by doing recipe parameter investigations and split lot analysis.

§         Proactively reduced particle defect mechanisms.

AWARDS:

2001 Intel Logic Technology Development Team Quality Award

In recognition of improving 0.13um process technology transistor performance by 5%

2000 Intel Technology Manufacturing Group Divisional Achievement Award

In recognition of solving N-Well sheet resistance excursion and implementing improved shallow silicon trench etch process

2000 Intel Technology Manufacturing Group Divisional Achievement Award

In recognition of serving on Material Review Board and saving more than 1 million die

1999 Intel Technology Manufacturing Group Divisional Achievement Award

In recognition of successful development and certification of 10% shrink of 0.35um technology process

SERVICE:

Reviewer for Journal of Vacuum Science Technology B

Reviewer for Electron, Ion, Photon Beam and Nanofabrication Conference 2010

Faculty Senate for Georgia Institute of Technology

Reviewer for Brookhaven National Laboratory

Review Panelist for National Science Foundation SBIR Program Phase I and II

Freddie Mac Foundation Wednesday’s Child Outreach

PUBLICATIONS:

Nicole R. Devlin, Devin K. Brown, "Fabricating millimeter to nanometer sized cavities concurrently for nanofluidic devices", Journal of Vacuum Science Technology B 28(6), Nov/Dec 2010

J. Blair, D. Brown, V.A. Tamma, W. Park, C. Summers, "Challenges in the fabrication of an optical frequency ground plane cloak consisting of silicon nanorod arrays", Journal of Vacuum Science Technology B 28(6), Nov/Dec 2010

N.R. Devlin, D.K. Brown, P. Kohl, “Patterning decomposable polynorbornene with electron beam lithography to create nanochannels”, Journal of Vacuum Science Technology B 27(6), Nov/Dec 2009, 2508

D.K. Brown, "Direct patterning of plasma enhanced chemical vapor deposition silicon dioxide by electron beam lithography" Journal of Vacuum Science Technology B 26(6), Nov/Dec 2008, 2451.

D.K. Brown, "Deep ultraviolet photolithography capability of ZEP520A electron beam resist for mix and match lithography" Journal of Vacuum Science Technology B 25(6), Nov/Dec 2007, 2447.

R. Murali, D.K. Brown, K.P. Martin, J.D. Meindl, “Improving electron beam resist sensitivity by preexposure to deep ultraviolet radiation,” Journal of Vacuum Science and Technology B, vol. 25, no. 6, pp. 2064-2067, Dec. 2007.

R. Murali, D.K. Brown, K.P. Martin, J.D. Meindl, "Process optimization and proximity effect correction for gray scale e-beam lithography," Journal of Vacuum Science & Technology B 24, 2936, 2006.

Zhiping Zhou, Devin K. Brown, Eric V. Woods, Akil K. Sutton, Biren C. Patel, Leslie O. George, “Optimization of contact interface resistance for CMOS circuits”, Proceedings of the 15th Biennial University/Government/Industry Microelectronics Symposium, 174-178 (2003).

PRESENTATIONS:

"Electron Beam Lithography Fabricated Carbon Nanofiber Water Analyzer", Nano@Tech Lecture, Sept. 22, 2009.  Online at http://hdl.handle.net/1853/30212

Momeni, B.; Soltani, M.; Askari, M.; Brown, D.K.; Adibi, A., “Ultra-compact preconditioned superprism-based photonic crystal demultiplexers”, 2005 IEEE LEOS Annual Meeting, p 198-9, 2005

S.P. Turano, D.K. Brown, V.S. Kumsomboone, W.J. Ready, “Electron Beam Lithography Patterned Substrates for Carbon Nanotube Growth”, 5th  Georgia Tech Nanoscience and Nanotechnology Conference, (2004).

SOFTWARE EXPERIENCE:

Matlab, Cadence, AutoCAD, LinkCAD, Unix, SAS JMP, LabView, CATS, HTML, Visual Basic, HP Basic, VMS DCL